Interconnect Scaling Implications for CAD

Abstract

Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are ode adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1999
Accession Number
ADA419604

Entities

People

  • Hema Kapadia
  • Ken Mai
  • Mark Horowitz
  • Ron Ho

Organizations

  • Stanford University

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Algorithms
  • Aspect Ratio
  • Capacitance
  • Computations
  • Demographic Cohorts
  • Dielectrics
  • Diffusion
  • Distribution Functions
  • Intervention
  • Load Distribution
  • Optimization
  • Resistance
  • Simulations
  • Standards
  • Statistical Analysis
  • Workload

Fields of Study

  • Physics

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Integrated Circuit Design and Technology.