The Future of Wires

Abstract

This chapter examines wire scaling and the capabilities of future wiring systems in more detail to better understand the constraints of these systems. If an existing circuit is scaled to a new technology, the relative change in the speed of wires versus the speed of gates is modest. Depending on one's assumptions about transistor performance under scaling, low-k dielectrics, and higher aspect ratio wires, the ratio is close to one. Thus the performance of today's IP cores should continue to improve with technology scaling. The key part of this scenario is that the length of the wire measured in gate pitches has remained constant, so its length in microns has scaled. The problem that designers face is not in needing to repartition current designs into smaller blocks, but rather that wire performance does not improve fast enough to make global communication on wires in a billion-transistor chip free. This global communication will be cheaper than in today's large board-level systems, but it will still take multiple cycles to send data across the chip. This constraint has already influenced some current designs and will lead to new architectures that are still wire-based, with partitioned resources and more explicit communication mechanisms. In this paper, the authors discuss the wire metrics of interest and examine them in a contemporary O.25 micrometer baseline technology, which has five to six layers of aluminum or copper interconnect, with upper metals wider and taller than lower metals. They then discuss technology scaling over the next several generations, from SIA and other predictions, and how wire metrics trend over that time. They also examine the delay and bandwidth limitations of both long global wires and short local wires and discuss architectural design techniques that help engineers avoid the limitations of scaled wires. (3 tables, 11 figures, 20 refs.)

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Document Details

Document Type
Technical Report
Publication Date
May 06, 1999
Accession Number
ADA419647

Entities

People

  • Ken Mai
  • Mark Horowitz
  • Ron Ho

Organizations

  • Stanford University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Aspect Ratio
  • Bandwidth
  • Capacitance
  • Capacitors
  • Circuits
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Couplings
  • Data Management
  • Demographic Cohorts
  • Dielectrics
  • Frequency
  • Global Communications
  • Metals
  • Power Supplies
  • Resistance

Readers

  • Computer Networking
  • Economics
  • Integrated Circuit Design and Technology.