A Delay Model for Router Micro-Architectures
Abstract
Current router models (2, 3, 5, 6) assume that clock cycle time depends solely on router latency. However, in practice, routers are heavily pipelined, making cycle time largely independent of router latency. In this paper, the authors describe a router delay model that accurately accounts for pipelining based on technology-independent delay estimates derived through detailed gate-level analysis. Simulations of realistic router pipelines show significant performance differences compared with the commonly-assumed unit-latency model. Using realistic pipeline models, they compared worm hole and virtual-channel flow control. The results show that virtual channels incur a modest additional cycle of per-hop router latency that is more than offset by the 25-40% throughput improvement over a wormhole router.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1999
- Accession Number
- ADA419650
Entities
People
- Bill Dally
- Li-shiuan Peh
Organizations
- Stanford University