Data Speculation Support for a Chip Multiprocessor
Abstract
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the support for thread- level speculation on the Hydra chip multiprocessor (CMP). The support consists of a number of software speculation control handlers and modifications to the shared secondary cache memory system of the CMP This support is evaluated using five representative integer applications. Our results show that the speculative support is only able to improve performance when there is a substantial amount of medium-grained loop-level parallelism in the application. When the granularity of parallelism is too small or there is little inherent parallelism in the application, the overhead of the software handlers overwhelms any potential performance benefits from speculative-thread parallelism. Overall, thread-level speculation still appears to he a promising approach for expanding the class of applications that can be automatically parallelized, but more hardware intensive implementations for managing speculation con- trol are required to achieve performance improvements on a wide class of integer applications.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1998
- Accession Number
- ADA419653
Entities
People
- Kunle Olukotun
- Lance Hammond
- Mark Wiley
Organizations
- Stanford University