Chip Multiprocessors Offer an Economical, Scalable Architecture for Future Microprocessors, Thread-Level Speculation Support Allows Them to Speed Up Past Software

Abstract

The Hydra chip multiprocessor (CMP) integrates four MIP-based processors and their primary caches on a single chip together with a shared secondary cache. A standard CMP offers implementation and performance advantages compared to wide-issue superscalar design& However, it must be programmed with a more complicated parallel programming model to obtain maximum performance. To simplify parallel programming, the Hydra CMP supports thread-level speculation and memory renaming, a paradigm that allows performance similar to a uniprocessor of comparable die area on integer programs. This article motivates the design of a CMP, describes the architecture of the Hydra design with a focus on its speculative thread support, and describes our prototype implementation.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 2000
Accession Number
ADA420740

Entities

People

  • Benedict A. Hubbert
  • Lance Hammond
  • Manohar K. Prabhu
  • Michael Chen
  • Michael Siu

Organizations

  • Stanford University

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Access Time
  • Clocks
  • Compilers
  • Computational Fluid Dynamics
  • Computer Programming
  • Computer Programs
  • Computers
  • Data Compression
  • Determinants (Mathematics)
  • Differential Equations
  • Digital Communications
  • Ear
  • Instructions
  • Partial Differential Equations
  • Procedures (Computers)
  • Simulations
  • Workload

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.