Asynchronous Techniques for Noise Tolerant Nanoelectronics
Abstract
The objective of this Phase I study was to demonstrate the advantages of asynchronous (clockless) VLST techniques with respect to noise tolerance, to determine the susceptibility of asynchronous QDI logic to noise-induced Single Event Upsets (SEU), and to propose solutions to detect and possible correct SEU errors. A logical model based on production rules was developed in which the effect of an SEU is represented as the random flipping of a single bit in the boolean representation of a circuit. Contrary to common belief, the study proves that an SEU will not necessarily lead to a deadlock, and that other forms of malfunctions may result: the circuit may duplicate an output or lose an input. Modifications to the circuit implementation of production rules have been proposed such that an SEU will always lead to deadlock. Further methods have ben developed to detect and correct single-bit upsets at the circuit level, with no change in system architecture, and little overhead on performance. In combination: with the natural tolerance of QDT circuits to slow parameter shifts and time variations, this study suggests that it is possible to build high-performance asynchronous hardware that is tolerant to noise.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 17, 2004
- Accession Number
- ADA423113
Entities
People
- Alain J. Martin
- Mika Nystroem