Applications of High Tc Planar Josephson Technology
Abstract
During this grant period we have taken our established single junction process to the next step in realizing a very large scale Josephson integrated circuit technology. We have made many process level improvements to address nonuniformity issues. We have fabricated identical junction pairs to study the mutual interactions between junctions. We have also fabricated arrays of 10, 50, and 100 junctions and have demonstrated a giant Shapiro step in the 10 junction case. Lastly we have updated and improved our measurement system and capabilities.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 29, 2004
- Accession Number
- ADA424063
Entities
People
- Robert C. Dynes
Organizations
- University of California, San Diego