Integrated Architectural Level Power-Performance Modeling Toolkit
Abstract
In this very simple study, we have assumed numbers representative of the order of magnitude of power dissipation for these classes of microprocessors; 0.5W for lowperf, 5W for midperf, and 50W for highperf. Future studies will use power models under development to perform more detailed analysis. The major thrust of our current work is to extend the scalability and flexibility of the powerperformance model and beginning to study the power-performance characteristics of multiple design points. Existing work has focused on scaling PowerTimer s power models for resource sizes 4 and pipeline depth 5. Our current efforts seek to maintain and improve the existing scalability models while also developing models for the following: Pipeline Width Similar to the pipeline depth, the fetch, dispatch, and retire width of the machine has a significant impact on the power-performance efficiency of the machine. Since pipeline width varies considerably between embedded and high-performance microarchitectures, this will be a key parameter that we will explore when studying the power-performance efficiency of design spaces. Multithreading and Chip Multiprocessing. Both simultaneous and coarse-grained multithreading have emerged as key microarchitectural techniques and detailed study of the power-performance efficiency of these schemes in the context of the other architectural parameters will be enlightening. In addition, the recent trend to multiple on-chip processor cores provides a rich area for power-performance tradeoffs for systems with sufficient thread-level parallelism.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 20, 2004
- Accession Number
- ADA428468
Entities
People
- David Brooks
Organizations
- Harvard University