Custom Reduction of Arithmetic in Linear DSP Transforms
Abstract
In multiplier-less hardware implementations of DSP transforms, multiplication-by-constants are implemented as a network of (wire-)shifts and additions. The number of additions required can be reduced by approximating the multiplicative constants using lower precision fixed-point representations, but the loss of precision increases the numerical error in the implementation. This trade-off can be leveraged to reduce the hardware area, critical path and power/energy while maintaining the perceptible quality of a signal processing application (e.g., MPEG-4). This paper describes an automatic approach to minimize the number of additions subject to a given quality measure, or, vice-versa, to maximize the quality subject to a given number of available additions. Our automatic approach can handle linear DSP transforms in general and includes optimizations over the space of algorithm design. A Verilog backend generates synthesizable descriptions of the final variable-width fixed-point implementations.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 23, 2003
- Accession Number
- ADA428795
Entities
People
- A. Zelinski
- James C. Hoe
- Markus Pueschel
- Smarahara Misra
Organizations
- Carnegie Mellon University