Cognitive Processing Hardware Elements Reconfigurable Architecture for Improved Soar Execution (RAISE)

Abstract

With help from Soar Technology, rule processing has been compared with both FPGAs and x8086 processors. For regular combinatorial logic, FPGAs present a speed-up of over x14000. However, they are presently unable to perform associative memory operations (pointer logic) that many rules require to operate. This shortcoming may be resolved with a dedicated memory management unit. The proof-of-concept RAISE system has been successfully designed and demonstrated. It uses a Virtex-II FPGA to implement a minor Soar application. A GUI allows users to send Working Memory Elements (WMEs) through a serial connection and receive results from the operators. The source code for the FPGA and GUI are in Appendices A and E. The first part of the Hoplite Guide to Run-time Reconfigurable Computing has been made available for free. Many have downloaded it and all comments have been positive.

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Document Details

Document Type
Technical Report
Publication Date
Feb 16, 2005
Accession Number
ADA430552

Entities

People

  • Matthew Scarpino
  • Robert Wray

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Algorithms
  • Circuits
  • Cognition
  • Computations
  • Computer Programming
  • Computer Programs
  • Content Addressable Memory
  • Contracts
  • Conversion
  • Department Of Defense
  • Field Programmable Gate Arrays
  • Graphical User Interface
  • Logic
  • Operating Systems
  • Serial Ports
  • Shift Registers
  • User Interface

Readers

  • Database Systems and Applications
  • Parallel and Distributed Computing.