A Systolic FFT Architecture for Real Time FPGA Systems
Abstract
MIT Lincoln Laboratory has recently developed a new systolic FFT architecture for FPGAs. This architecture utilizes a parallel design to provide high throughput and excellent numerical accuracy. Using this design, an 8192-point real-time FFT, operating at 1.2 billion samples per second and performing 78 Gops with 70 dB of accuracy, fits on a single Xilinx Virtex II 8000.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 2005
- Accession Number
- ADA433002
Entities
People
- Charles M. Rader
- Cy P. Chan
- Jonathan E. Scalera
- M. M. Vai
- Preston A. Jackson
Organizations
- Massachusetts Institute of Technology