Variable Precision Floating Point Division and Square Root
Abstract
Division and square root are important operations in many high performance signal processing applications including matrix inversion, vector normalization, least squares lattice filters and Cholesky decomposition. We have implemented floating point division and square root designs for our VHDL variable precision floating point library. These designs are implemented in VHDL and are designed to make efficient use of FPGA hardware. Both the division 1 and square root 2 algorithms are based on table lookup and Taylor series expansion. These algorithms are particularly well-suited for implementation on an FPGA with embedded RAM and embedded multipliers such as the Altera Stratic and Xilinx Virtex2 devices. The division and square root components have been incorporated into the framework of our variable precision floating-point library.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 2005
- Accession Number
- ADA433087
Entities
People
- Miriam Leeser
- Xiaojun Wang
Organizations
- Northeastern University