Discrete Fourier Transform IP Generator

Abstract

Intellectual Property (IP) libraries are commonly used by hardware designers to increase productivity and reduce the time-to-market. These static IP libraries do not allow the designers flexibility in customizing trade-offs. We propose a parameterized DSP IP generator that allows designers to specify the cost/performance tradeoff. We present a prototype implementation of a parameterized DFT generator and compare our generated DFT with Xilinx LogiCore's DFT IP Core. Our results show that we generate high-quality DFT blocks that match the performance and cost of Xilinx LogiCore DFT implementations. More importantly, we show that our parameterized design generation yields customized DFT blocks over a range of different performance/cost tradeoff points.

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Document Details

Document Type
Technical Report
Publication Date
Sep 30, 2004
Accession Number
ADA433153

Entities

People

  • Grace Nordin
  • James C. Hoe
  • Markus Pueschel

Organizations

  • Carnegie Mellon University

Tags

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Computers
  • Demographic Cohorts
  • Discrete Fourier Transforms
  • Energy Consumption
  • Engineering
  • Generators
  • Information Operations
  • Intellectual Property
  • Logic
  • Mathematics
  • Microarchitecture
  • Permutations
  • Prototypes
  • Shift Registers
  • Throughput

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.
  • Quantum Chemistry
  • Software Engineering.