Processing Challenges in Shrinking HPEC Systems into Small UAVs
Abstract
The best-known unmanned aerial vehicles (UAVs), Predator and Global Hawk, are large, multi-million dollar aircraft managed as theater/national assets. With synthetic aperture radar (SAR), electro-optic/infrared (EO/IR), and signals intelligence (SIGINT) payloads, these UAVs have proven their worth in battlefields from Bosnia to Afghanistan and Iraq. This success has led to a surge in proposed UAV missions and designs using a layered approach with multiple classes of UAVs to provide persistent narrow and wide ISR (intelligence, surveillance, reconnaissance) coverage. Programs such as the Future Combat System (FCS) include a large role for tactical UAVs, small UAVs, and unmanned ground vehicles (UGVs). The smaller, cheaper unmanned vehicles can be deployed at the brigade or company level to see over the next hill. With many vehicles and many sensors, network bandwidth becomes an issue. So future UAVs will include aided/automatic target recognition (AiTR/ATR) capabilities to reduce both communication bandwidth and latency. Large UAVs such as Global Hawk and Predator have been successful using today's HPEC solutions. Global Hawk currently uses a 9U VME system with PowerPC processors for SAR and EO/IR processing, while the Predator is a bit smaller, using a 6U VME system for TESAR processing. The challenge is to provide similar processing power for much smaller UAVs, many of which have less than 1/2 the payload weight and 1/4 the volume of the Predator. This presentation will provide a detailed set of trade-offs in computational capabilities, I/O capabilities, and memory capacities distributed between FPGAs and Power PCs for sample applications of SAR image formation and SIGINT channelized receiver throughout.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 28, 2004
- Accession Number
- ADA433160
Entities
People
- Richard Jaenicke
- Stephen Pearce