Versatile Tiled-Processor Architectures: The Raw Approach
Abstract
This presentation will describe the Raw architecture, its implementation, and performance. We will focus on Raw's ability to support a diverse set of applications (ranging from desktop to embedded workloads) and multiple forms of parallelism (including instruction-level parallelism (ILP) for desktop applications, and stream parallelism for embedded computing) as represented by the VersaBench suite. We will also report detailed performance measurements that quantify the versatility of Raw compared to some widely deployed architectures. As a prelude, the measured versatility of the Raw processor is 0.7, while that of the Pentium III is 0.1. The Pentium's relatively poor performance on stream benchmarks hurts its versatility. Although Raw's versatility is better in comparison, the VersaBench suite highlights two clear areas that merit additional research. The first is in improving the architecture to better support embedded bit-level workloads: ASICs perform 2x-3x better than Raw. Another area of research focuses on desktop integer applications: Raw's performance is 2x lower than a Pentium III for applications with low degrees of ILP.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 30, 2004
- Accession Number
- ADA433161
Entities
People
- Anant Agarwal
- Ian Bratt
- Krste Asanovic
- Rodric M. Rabbah
Organizations
- Massachusetts Institute of Technology