Automated Incremental Design of Flexible Intrusion Detection Systems on FPGAs
Abstract
Intrusion detection for network security is a computeintensive application demanding high system performance. This paper presents a variety of strategies we have developed for the automatic synthesis of highly efficient intrusion detection systems. We create FPGA architectures using a high-level, graph-based partitioning methodology. We provide a library of performancecustomized architectures, which, through more efficient communication and extensive reuse of hardware components, provide dramatic increases in area-time performance. This paper addresses a problem of earlier designs, the requirement for complete place-and-route for small changes to the pattern database, through an optimized incremental design strategy.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 01, 2005
- Accession Number
- ADA433586
Entities
People
- Viktor K. Prasanna
- Zacahry Z. Baker
Organizations
- University of California, Los Angeles