Scaling Prospects for Ultimate Nanotransistors
Abstract
Advanced semiconductor field-effect transistors (FET), scaled into the sub-10-nm gate length range, are sometimes considered the main candidates for future nanoelectronics, even beyond the long-term horizon of the International Technology Roadmap for Semiconductors. In this project, the long-term prospects of FET scaling were evaluated in greater detail than ever before. In particular, the authors have calculated the source-drain I-V curves, subthreshold characteristics, voltage gain, and power consumption of sub-10-nm, double-gate silicon MOSFETs using the self-consistent solution of quasi-2D Schroedinger and 2D Poisson equations. Most importantly, the sensitivity of the transistor's characteristics (in particular, the gate voltage threshold) to variations in structure dimensions were evaluated in detail. The results show that this sensitivity, which strongly affects the fabrication facilities costs, sets the ultimate limits for CMOS technology scaling. Based on the results, this limit is close to 10-nm gate length for single-gate transistors and 8-nm gate length for double-gate transistors. Further continuation of the Moore Law development of microelectronics will probably require a transfer to integrated circuits based on CMOS/nanodevice hybrids.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 31, 2005
- Accession Number
- ADA434579
Entities
People
- Konstantin K. Likharev
Organizations
- State University of New York