Pipelined Delta Sigma Modulator Analog to Digital Converter for SOC Applications

Abstract

A two-stage Pipelined Delta Sigma Modulator analog-to-digital converter is presented for broad band, high resolution System-on-a-Chip (SOC) applications. Input bandwidth is 62.5 MHz and the sampling frequency of 1 GHz results in an oversampling ratio of 8, and a 12-bit resolution with a 50 MHz input.

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Document Details

Document Type
Technical Report
Publication Date
Apr 01, 2005
Accession Number
ADA435208

Entities

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  • Ray Siferd
  • Robert Blumgold
  • Saiyu Ren

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