Microarchitectural Floorplanning for Thermal Management: A Technical Report
Abstract
In current day microprocessors, exponentially increasing power densities, leakage, cooling costs, and reliability concerns have resulted in temperature becoming a first class design constraint like performance and power. Hence, virtually every high performance microprocessor uses a combination of an elaborate thermal package and some form of Dynamic Thermal Management (DTM) scheme that adaptively controls its temperature. While DTM schemes exploit the important variable of power density to control temperature, this paper attempts to show that there is a significant peak temperature reduction potential in managing lateral heat spreading through floorplanning. It argues that this potential warrants consideration of the temperature-performance trade-off early in the design stage at the microarchitectural level using floorplanning. As a demonstration, it uses previously proposed wire delay model and floorplanning algorithm based on simulated annealing to present a profile-driven, thermal-aware floorplanning scheme that significantly reduces peak processor temperature with minimal performance impact that is quite competitive with DTM.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 20, 2005
- Accession Number
- ADA436653
Entities
People
- Karthik Sankaranarayanan
- Kevin Skadron
- Mircea R. Stan
- Sivakumar Velusamy
Organizations
- University of Virginia