The Torus Routing Chip

Abstract

The torus routing chip (TRC) is a self-timed chip that performs deadlock-free cut-through routing in k-ary n-cube multiprocessor interconnection networks using a new method of deadlock avoidance called virtual channels. A prototype TRC with byte wide self-timed communication channels achieved on first silicon a throughput of 64Mbits/s in each dimension, about an order of magnitude better performance than the communication networks used by machines such as the Caltech Cosmic Cube or Intel iPSC. The latency of the cut-through routing of only l5Ons per routing step largely eliminates message locality considerations in the concurrent programs for such machines. The design and testing of the TRC as a self-timed chip was no more difficult than it would have been for a synchronous chip.

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Document Details

Document Type
Technical Report
Publication Date
Jan 24, 1986
Accession Number
ADA442968

Entities

People

  • Bill Dally
  • Charles L. Seitz

Organizations

  • California Institute of Technology

Tags

DTIC Thesaurus Topics

  • Abstracts
  • Availability
  • Classification
  • Communication Channels
  • Communication Networks
  • Contracts
  • Information Operations
  • Instructions
  • Monitoring
  • Multiprocessors
  • Networks
  • Prototypes
  • Security
  • Standards

Fields of Study

  • Computer science

Readers

  • Graph Algorithms and Convex Optimization.
  • Parallel and Distributed Computing.