A Synthesis Method for Self-Timed VLSI Circuits
Abstract
With chip size reaching 1 million transistors, the need for high-level design of circuits becomes compelling. The main stumbling block in the development of design methods for VLSI algorithms is to find an interface that provides a good separation of the physical and algorithmic concerns. Among the physical issues, timing is the most-critical, since it is not only essential to the real-time behavior of a circuit, but also to its logical correctness if synchronous techniques are used. Synchronous techniques are detrimental to the use of high-level design methods because they don't "scale well" a circuit may cease to function correctly when its feature aisles are scaled down to smaller dimensions. Further, with the increasing size of circuits, it becomes more and more difficult to distribute safely a clock signal across a chip, and the restrictions attached to wire lengths in order to maintain certain timing properties add extra complication to the already difficult layout problem.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1987
- Accession Number
- ADA444293
Entities
People
- Alain J. Martin
Organizations
- California Institute of Technology