Interconnect Synthesis for Systems on Chip

Abstract

We describe an algorithm for performing a joint scheduling/ interconnect synthesis optimization for System-on-Chip (SoC) architectures. The algorithm is able to account for different distributions of long vs. short interconnect routes in an architecture. It is based on a genetic algorithm, and utilizes a graph isomorphism test to significantly pare the search space and increase the search efficiency.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 2004
Accession Number
ADA448078

Entities

People

  • Neal K. Bambha
  • Shuvra S. Bhattacharyya

Organizations

  • University of Maryland

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Chromosomes
  • Computations
  • Computers
  • Demographic Cohorts
  • Detectors
  • Embedded Systems
  • Energy Consumption
  • Engineering
  • Equations
  • Genetic Algorithms
  • Mutations
  • Optical Interconnects
  • Scheduling (Production)
  • Topology
  • Universities

Fields of Study

  • Computer science

Readers

  • Integrated Circuit Design and Technology.
  • Operations Research

Technology Areas

  • AI & ML
  • AI & ML - Machine Learning Algorithms
  • Biotechnology
  • Space
  • Space - Space Objects