An FPGA Implementation of ATR Using Embedded Ram for Control

Abstract

Automatic Target Recognition (ATR) is a computationally intensive problem with potential for good performance when mapped to Field Programmable Gate Arrays (FPGAs). This thesis presents work that was done to implement the Sandia National Laboratory Chunky SLD stage of ATR on an Altera FLEX 10K50. The FLEX 10K series has large (256 x 8), dedicated, embedded memories that present an opportunity for unique and innovative implementations of computing algorithms. These memories were used for several purposes; the most interesting use was to store microinstructions that direct the operation of the ATR processor. With this method of implementing Chunky SLD, good performance was achieved relative to other FPGA and microprocessor implementations.

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Document Details

Document Type
Technical Report
Publication Date
Jun 30, 1997
Accession Number
ADA449851

Entities

People

  • Richard D. Ross

Organizations

  • Brigham Young University

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes
  • Space

DTIC Thesaurus Topics

  • Algorithms
  • Automatic
  • Coding
  • Computer Programming
  • Computer Programs
  • Computers
  • Detection
  • Field Programmable Gate Arrays
  • Identification
  • Logic Elements
  • Microcode
  • Pattern Recognition
  • Probability
  • Recognition
  • Synthetic Aperture Radar
  • Target Recognition
  • Two Dimensional

Readers

  • Computer Vision.
  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.