A Delay-Insensitive Multiply-Accumulate Unit
Abstract
Due to advances in integration technology the use of asynchronous circuits has become increasingly interesting. Design methods have emerged with which it is manageable to design efficient and reliable asynchronous circuits. Instead of designing circuits under worst case assumptions as for synchronous circuits, the objective in asynchronous design is to attain the best possible average performance and to utilize this potential performance advantage at the architectural level. We have designed a serial-parallel multiply-accumulate unit that exploits this performance advantage. The unit is designed to be part of a large ring network of units performing vector-matrix multiplications.
Document Details
- Document Type
- Technical Report
- Publication Date
- Feb 12, 1992
- Accession Number
- ADA451173
Entities
People
- Alain J. Martin
- Christian D. Nielsen
Organizations
- California Institute of Technology