VLSI Design of High-Speed Time-Recursive 2-D DCT/IDCT Processor for Video Applications

Abstract

In this paper we present a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to prove its performance. We show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. Our design of the 8 x 8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2 mu CMOS technology. In comparison to the existing designs, our approach offers many advantages that can be further explored for even higher performance.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1994
Accession Number
ADA455511

Entities

People

  • K. J. Ray Liu
  • Vishnu Srinivasan

Organizations

  • University of Maryland

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Fields of Study

  • Computer science
  • Engineering

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  • Computer Networking
  • Integrated Circuit Design and Technology.
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