Mixed Signal Receiver-on-a-Chip RF Front-End Receiver-on-a-Chip
Abstract
The primary goal for the RoC project is to demonstrate highly integrated mixed signal ICs employing the advanced silicon germanium (SiGe) technology. To that end, the MSDT designed two integrated chipsets for a double down conversion receiver architecture with frequency operation ranging from X to L Bands. This report describes the first integrated chipset (IC1) of the receiver block. The updated system architecture of IC1 and the associated layout, shown in Figures 4 and 5, illustrates a single down conversion configuration operating from X to S-Band. Components in IC1 are X-Band Low noise amplifier, lead lag balun, balanced amplifier, double-balanced diode mixer, bandpass filter, and a buffer amplifier. The IC1 chip was packaged in a Precision Multi-Chip Module technology (P-MCM) using the flip chip fabrication process. Measurements of the packaged IC1 chip, achieved 22-23 dB gain across the first IF frequency of 3.7-4.3 GHz. The targeted application for the SiGe chipset is the Scalable Panels for Efficient and Affordable Radar and UAV programs where the primary drivers are reduction in cost, size, and power while maintaining performance. The successful demonstration of the SiGe chip represents a first pass design success of a highly complex receiver front-end chipset with State of the Art performance.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 01, 2006
- Accession Number
- ADA456359
Entities
People
- Aji Mattamana
- Gregory Creech
- Pompei Orlando
- Scott Axtell
- Tony Quach
- Vipul J. Patel
Organizations
- Air Force Research Laboratory