A Fault-Tolerant Multiprocessor Architecture for Digital Signal Processing Applications
Abstract
Proposed is a fault-tolerant multiprocessor architecture which needs much less redundant hardware than Modular Redundancy architectures. The architecture uses weighted checksum techniques and is suited for linear Digital Signal Processing applications in which multiple copies of the identical processor are used to meet the through- put requirement. Single fault detection/correction and multiple detection/correction techniques are discussed. Also proposed are statistical fault detection/correction algorithms for systems containing numerical roundoff or truncation noise such as fixed point or floating point systems. Presented are the simulations of these algorithms as well as the simulations of numerical noise distributions in real fixed point system applications. Our choice of weights reduces the dynamic range requirement of the checksum processors arid minimizes the masking of small faults by the numerical noise. Efficient fault detection/correction algorithms for the exact arithmetic systems are presented, including one for residue arithmetic systems. Practical architectures for implementing the single fault detection/correction algorithm are also presented. These architectures are designed to mask any single component failure in the system.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jan 01, 1989
- Accession Number
- ADA458650
Entities
People
- William S. Song
Organizations
- Massachusetts Institute of Technology