Procedural Layout of a High-Speed Floating-Point Arithmetic Unit

Abstract

This thesis presents a case study in the procedural design of the layout of a complex digital circuit. This is the task of writing a program which constructs a VLSI circuit layout given a set of variable parameters which specify the desired functionality of the circuit. We present a set of techniques for guaranteeing that the constructed circuit obeys the geometric and electrical design rules imposed by the underlying circuit technology. These include a set of simple circuit forms and composition rules for building precharged combinatorial circuits which are free of critical race conditions and charge-sharing problems. As an example, we carry out the creation of a program for building a floating-point addition unit which has selectable number of bits of exponent and fraction in the floating-point representation. The high-level design of a companion floating-point multiplication unit is also discussed.

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Document Details

Document Type
Technical Report
Publication Date
Jun 01, 1985
Accession Number
ADA459612

Entities

People

  • Robert C. Armstrong

Organizations

  • Massachusetts Institute of Technology

Tags

Communities of Interest

  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Air Force
  • Arithmetic
  • Arithmetic Units
  • Computer Programs
  • Computers
  • Databases
  • Electrical Engineering
  • Floating Point Operations
  • Intellectual Property
  • Lists (Data Structures)
  • Logic
  • Logic Gates
  • Network Protocols
  • Signal Processing
  • Simulators
  • Topology
  • Xor Gates

Fields of Study

  • Engineering

Readers

  • Approximation Theory.
  • Database Systems and Applications
  • Integrated Circuit Design and Technology.