Code Compression for DSP

Abstract

Previous works have proposed adding compression techniques to a variety of architectural styles to reduce instruction memory requirements. It is not immediately clear how these results apply to DSP architectures. DSP instructions are longer and have potentially greater variation which can decrease compression ratio. Our results demonstrate that DSP programs do provide sufficient repetition for compression algorithms. We propose a compression method and apply it to SHARC, a popular DSP architecture. Even using a very simple compression algorithm, it is possible to halve the size of the instruction memory requirements.

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Document Details

Document Type
Technical Report
Publication Date
Dec 01, 1998
Accession Number
ADA461522

Entities

People

  • Charles Lefurgy
  • Trevor Mudge

Organizations

  • University of Michigan

Tags

DTIC Thesaurus Topics

  • Algorithms
  • Coding
  • Compression
  • Compression Ratio
  • Computer Programming
  • Computer Science
  • Computers
  • Computing System Architectures
  • Data Compression
  • Digital Signal Processing
  • Electrical Engineering
  • Engineering
  • Information Operations
  • Instructions
  • Optimization
  • Programming Languages
  • Signal Processing

Fields of Study

  • Computer science

Readers

  • Computational Modeling and Simulation
  • Mechanical Engineering/Mechanics of Materials.
  • Parallel and Distributed Computing.