Feasibility Study of Nanoscale Semiconductor Manufacture Using Thermal Dip Pen Nanolithography
Abstract
This one-year feasibility study explored the use of thermal dip-pen nanolithography (DPN) for the purpose of nanoscale electronics manufacturing. In this project, we have demonstrated that using the thermal DPN technique that both indium metal, and semiconducting organic materials (PDDT, PVDF) can be written in arbitrary locations on semiconductor surfaces with sub-100 nm feature sizes. We have measured the electrical properties of these nanostructure deposits and found them to be electrically functional. This accomplishment opens new opportunities for nanoelectroopics manufacture and repair, where a functional deposit of an electronic material can be deposited in an arbitrary single location. Thus we can report success in this feasibility study.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 30, 2006
- Accession Number
- ADA463608
Entities
People
- William P King
Organizations
- Georgia Tech Research Corporation