Impact of Parameter Variations on Multi-Core Chips

Abstract

Increasing variability during manufacturing and during runtime are projected for future generation microprocessors. This paper introduces a pre-RTL, architectural modeling methodology that incorporates the impact of manufacturing and runtime temperature variations on delay and power for both combinational logic and SRAM structures. The model is then used to show that frequency variations among microarchitectural functional units and among cores are relatively small in a high-performance microprocessor design. However, the impact of within-die systematic process variations on leakage power will result in major leakage variation across multiple cores on a single chip. WID leakage variation can cause core-to-core leakage to differ by as much as 45%.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2006
Accession Number
ADA465191

Entities

People

  • David Tarjan
  • Eric Humenay
  • Kevin Skadron

Organizations

  • University of Virginia

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Abstracts
  • Access Time
  • Circuits
  • Computer Architecture
  • Computer Science
  • Computers
  • Computing System Architectures
  • Electronics
  • Fabrication
  • Frequency
  • Manufacturing
  • Microprocessors
  • Power Electronics
  • Semiconductor Manufacturing
  • Semiconductors
  • Solid State Electronics
  • Transistors

Fields of Study

  • Engineering

Readers

  • Integrated Circuit Design and Technology.
  • Mathematics or Statistics
  • Parallel and Distributed Computing.