An 18-GHz, 10.9-dBm Fully-Integrated Power Amplifier with 23.5% PAE in 130-nm CMOS
Abstract
An 18-GHz fully integrated class-E power amplifier with 10.9-dBm saturated output power and 23.5% maximum power added efficiency (PAE) was fabricated in the UMC 130-nm digital complementary metal-oxide semiconductor (CMOS) process. At the saturated output the required input power level is -5dBm and the power amplifier consumes 35mA from V(sub DD)=1.5V. The amplifier is single-ended and includes a 2-stage pre-amplifier and a driver stage. A mode-locking technique exploiting the instability of the driver amplifier is used to improve the drive for the gate of output stage. The mode-locking improves PAE by approximately 3% and reduces the required input power level by approximately 6dB to get the same output level. The performance of the power amplifier in this work is compared to that of previously reported power amplifiers operating near 20GHz. The results show that this power amplifier shows significantly higher efficiency and lower input requirements than that of the CMOS power amplifiers operating at 20GHz. The research suggests that CMOS technology is a viable candidate for building a fully integrated transmitter near 20GHz.
Document Details
- Document Type
- Technical Report
- Publication Date
- Sep 01, 2005
- Accession Number
- ADA465241
Entities
People
- Changhua Cao
- Haifeng Xu
- Kenneth K. O.
- Yu Su
Organizations
- University of Florida