Parallel Simulation of Chip-Multiprocessor Architectures

Abstract

Chip-multiprocessor (CMP) architectures present a challenge for efficient simulation, combining the requirements of a detailed microprocessor simulator with that of a tightly-coupled parallel system. In this paper, a distributed simulator for target CMPs is presented based on the Message Passing Interface (MPI) designed to run on a host cluster of workstations. Microbenchmark-based evaluation is used to narrow the parallelization design space concerning the performance impact of distributed vs. centralized target L2 simulation, blocking vs. non-blocking remote cache accesses, null-message vs. barrier techniques for clock synchronization, and network interconnect selection. The best combination is shown to yield speedups of up to 16 on a 9-node cluster of dual-CPU workstations, partially due to cache effects.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 2002
Accession Number
ADA466301

Entities

People

  • Alan D. George
  • Matthew C. Chidester

Organizations

  • University of Florida

Tags

Communities of Interest

  • Advanced Electronics
  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Access Time
  • Accuracy
  • Algorithms
  • Clocks
  • Computer Programming
  • Computers
  • Computing System Architectures
  • Digital Communications
  • High Performance Computing
  • Instructions
  • Microprocessors
  • Multiprocessors
  • Simulations
  • Simulators
  • Test And Evaluation
  • Workload

Fields of Study

  • Computer science
  • Engineering

Readers

  • Parallel and Distributed Computing.

Technology Areas

  • Space