Ultra-Low-Energy Sub-Threshold Circuits: Program Overview
Abstract
In this DARPA program, we have developed a robust design methodology to scale power supply voltages to levels as low as 250mV, reducing the energy dissipation of digital computation by an order of magnitude. We have demonstrated both logic (standard cells) and memory. We have explored the use of parallelism to maintain performance at reduced power supply voltages. This concept was demonstrated with a UWB baseband processor. We have developed a DC-DC converter to efficiently deliver sub-threshold voltage and minimize the power dissipation of an arbitrary digital circuit. We have demonstrated 9 test chips in state-of-the-art 65nm, 90nm and 0.18 micrometers CMOS technologies. All test chips were fabricated for free (primarily by TI).
Document Details
- Document Type
- Technical Report
- Publication Date
- Apr 10, 2007
- Accession Number
- ADA469416
Entities
People
- Anantha Chandrakasan
Organizations
- Defense Advanced Research Projects Agency