Design and Simulation of a Programmable Memory/Multiplier Array Using G4-FET Technology

Abstract

Field-programmable and mask-programmable gate arrays can greatly reduce the non-recurring costs of ASIC development by reusing both masks and physical design effort across many designs. The downside of gate arrays is that they result in suboptimal implementations in terms of area, speed, and power. In addition, there is very little flexibility in converting logic to memory or vice versa, a problem of increasing importance as memory-intensive applications gain in importance. To address these issues, we have investigated the design of a novel gate array structare based on G4-FET devices, which combine SOI CMOS and JFET technologies, and that can be biased to function as either a not-majority logic gate, a router/multiplexer, or as a DRAM cell. To demonstrate the potential of G4-FETs for gate arrays, we have designed a memory/multiplexer array that consists of an array of configurable cells built from G4-FETs and a mask-configurable interconnect that may serve as either a multiply-accumulate circuit or as a memory array.

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Document Details

Document Type
Technical Report
Publication Date
Jul 01, 2007
Accession Number
ADA470480

Entities

People

  • Jay B. Brockman
  • Peter M. Kogge

Organizations

  • University of Notre Dame

Tags

DTIC Thesaurus Topics

  • Air Force Research Laboratories
  • Circuits
  • Complementary Metal-Oxide Semiconductors
  • Computer-Aided Design
  • Digital Circuits
  • Electronics Laboratories
  • Field Effect Transistors
  • Field Programmable Gate Arrays
  • Governments
  • Logic
  • Logic Devices
  • Logic Gates
  • Low Voltage
  • Metal Oxide Semiconductors
  • Semiconductors
  • Simulations
  • Standards

Fields of Study

  • Engineering

Readers

  • Educational Psychology
  • Integrated Circuit Design and Technology.