Field Programmable Gate Array Based Global Communication Channel for Digital Signal Processor Chips
Abstract
An apparatus comprising a host digital signal processor (DSP), at least one field programmable gate array (FPGA) in communication with the host DSP for receiving a digital signal from the host DSP, and at least one non-host DSP in communication with the at least one FPGA for receiving the digital signal.
Document Details
- Document Type
- Technical Report
- Publication Date
- Jul 11, 2005
- Accession Number
- ADA471400
Entities
People
- C. R. Dutton
Organizations
- United States Department of the Navy