Silencer! A Tool for Substrate Noise Coupling Analysis

Abstract

This thesis presents Silencer!, a fully automated, schematic-driven tool for substrate noise coupling simulation and analysis. It has been integrated into the CADENCE DFII environment and seamlessly enables substrate coupling analysis in a standard mixed-signal design flow. Silencer! aids IC designers in the analysis of substrate noise coupling at different levels of hierarchy -- from a level where only an approximate layout of the transistors is known to a level that incorporates various parasitic elements. It can be used for layout optimization to reduce substrate cross-talk noise between circuitry that injects noise into the substrate and other circuitry that is sensitive to it. Examples in a TSMC 0.35 micrometer heavily doped process have been simulated and the results are in good agreement with measured fabricated chips.

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Document Details

Document Type
Technical Report
Publication Date
Jan 09, 2004
Accession Number
ADA471474

Entities

People

  • Patrick Birrer

Organizations

  • Oregon State University

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Amplifiers
  • Capacitance
  • Computers
  • Couplings
  • Digital Circuits
  • Electrical Engineering
  • Electronic Equipment
  • Engineering
  • Environment
  • Hierarchies
  • Power Supplies
  • Simulations
  • Simulators
  • Standards
  • Transistors
  • Two Dimensional
  • User Interface

Fields of Study

  • Engineering

Readers

  • Acoustics.
  • Database Systems and Applications
  • Integrated Circuit Design and Technology.