Modeling Phase-Locked Loops Using Verilog
Abstract
An essential component of any mixed signal embedded system is a Phase-Locked Loop (commonly know as PLL). Almost every mixed signal system has one or more PLL in its block diagram. Phase-locked loops are used for a variety of tasks, like multiplying clock frequencies, generating precise clock phases, and generating complex RF modulated signals like phase modulation. Many modern field programmable gate array devices come with integrated PLL to multiply clocks or adjust the phase of clock outputs. Modeling PLLs has always been difficult because they are part analog and part digital. Circuits that are both analog and digital are called "Analog Mixed Signal" or abbreviated as AMS. In the most basic block diagram of a PLL (Figure 1), the building blocks of the PLL are identified. The voltage-controlled oscillator (or VCO), the charge pump (or loop amplifier), and the loop filter are all analog blocks. The phase detector and dividers are digital blocks. Because the PLL is composed of both analog and digital blocks, it is called mixed signal. The PLL is a feedback loop that adjusts the phase and frequency of the VCO to lock to the phase of the input reference oscillator. When the PLL is locked, the output frequency is a fractional multiple of the input frequency, equation F(out) / N = F(ref) / R or F(out) = F(ref) N / R.
Document Details
- Document Type
- Technical Report
- Publication Date
- Nov 01, 2007
- Accession Number
- ADA483891
Entities
People
- Jeffrey Meyer