Comparing Throughput and Power Consumption in Sequential and Reconfigurable Processors
Abstract
This research project involves an investigation of parallel processing using reconfigurable logic devices. The goal of this project is to support the Naval Research Labs' recent acquisition of a Cray XD-1 supercomputer. A feature of the Cray XD-1 is that it contains field programmable gate arrays (FPGAs). These reconfigurable devices contain hardware whose connections can be modified to target a specific computation. This adaptability can significantly improve the processing speed of computationally intensive operations. Recent improvements in the memory capacity of FPGAs have spurred interest in using the devices for arithmetic floating-point operations using the IEEE 754 standard. In this project, a high-level language (HLL)--Mitrion-C 1.4--was used to reduce some of this effort. Using this language, two calculations taken from a ray-tracing simulation of NASA's Moderate Resolution Imaging Spectroradiometer (MODIS) were implemented on an FPGA. The calculations consisted of floating-point additions, subtractions, multiplications, divisions, and square root extractions. It was feasible to perform many of the calculations in parallel, leading to a substantial increase in system throughput. Functionally identical programs were also implemented on a sequential processor--an Opteron 275--using the American National Standards Institute s standard for C (ANSI-C). Those portions of the FPGA design and of the sequential programs that were dedicated to performing scientific calculations were isolated and their processing time was measured using functions written in ANSI-C and calculated by the sequential processor. In addition, power consumption was measured both while the FPGA hardware implementation ran and while the sequential program ran. The results showed that implementing the two calculations on an FPGA was about 900% faster than a sequential processor, requiring only roughly a 30% increase in power consumed.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 05, 2008
- Accession Number
- ADA486712
Entities
People
- Kevin K. Liu
Organizations
- United States Naval Academy