Fault Tolerant Microcontroller for the Configurable Fault Tolerant Processor

Abstract

In this thesis, the design of a fault tolerant microcontroller for the Configurable Fault Tolerant Processor is presented. The Configurable Fault Tolerant processor is a spaceborne Field Programmable Gate Array experiment platform susceptible to Single Event Upsets. Fault tolerance is needed to control the experiment in higher radiation orbits and the microcontroller will offer enhanced functionality for experiments. The 16-bit microcontroller is contained within the resources of a single Field Programmable Gate Array. It includes RAM, microprocessor, FPGA configuration and configuration readback modules, PC/104 interface module, and fault detection and correction capabilities. Fault tolerance is implemented via triple modular redundancy and Hamming error correction coding. Complete source code for the microcontroller and C-based compilation tools are included as appendices.

Open PDF

Document Details

Document Type
Technical Report
Publication Date
Sep 01, 2008
Accession Number
ADA488702

Entities

People

  • David E. Dwiggins Jr.

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Advanced Electronics
  • Space

DTIC Thesaurus Topics

  • Artificial Satellites
  • Circuits
  • Coding
  • Computer Programming
  • Computer Programs
  • Computers
  • Decoding
  • Detection
  • Fault Tolerance
  • Field Programmable Gate Arrays
  • Graphical User Interface
  • Instruction Set Architecture
  • Integrated Circuits
  • Operating Systems
  • Software Development
  • Space Systems
  • United States Naval Academy

Fields of Study

  • Physics

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.

Technology Areas

  • Space