Hardware, Software and Data Analysis Techniques for SRAM-based Field Programmable Gate Array Circuits
Abstract
The main objective of this research is to accomplish two objectives; first, develop a robust test methodology to successfully allow researchers to isolate errors occurring in SRAM-based FPGAs and other memory devices. Second, provide a test platform capable of exercising this methodology. Several requirements were made known for this platform. The system should be compact, versatile, flexible, and affordable. To meet these objectives, a failure analysis tree was derived such that various combinations of circuits on a test FPGA, with subsequent data analysis being accomplished on a controller FPGA board. Using the data derived from various types of adder and counter circuits, major subsystems of the FPGA could be targeted. Next, a test structure was built using a controlling FPGA board and a laptop for data reporting. The controller board provided stimuli to the device under test (DUT), accepted the data produced, and automatically analyzed the data to generate data messages. Additionally, Xilinx BlockRam modules were created to test their susceptibility to logic errors in a radiation environment. Two reliability-enhancing techniques were implemented for evaluation; triple modular redundancy (TMR) and error correction coding (ECC).
Document Details
- Document Type
- Technical Report
- Publication Date
- Jun 01, 2008
- Accession Number
- ADA489580
Entities
People
- Eugene B. Hockenberry
Organizations
- Air Force Institute of Technology