Power Efficient Radar Signal Processor
Abstract
Power efficiency and ease of programming are key issues in the implementation of real-time systems in airborne and space-based applications. This paper describes a radiation tolerant processor designed for space-based Radar applications. The proposed system achieves real-time performance while minimizing power consumption. It is a fully programmable general purpose processor that can be used for existing and future Radar signal processing algorithms as well as other computationally intensive tasks. In addition to programmability, the processor and I/O design facilitate scaling to thousands of processors. The system is based on synthesizable VHDL and can be Radiation hardened by design or by process technology. This paper gives an overview of the processor design. Further, it explains the software environment and tools available for the programmers. All of the software tools are open source and many are based on the GNU tools. [1] In this paper we present the performance of some of the key routines such as Fast Fourier Transform, and Householder Q/R factorization used for matrix inversion. Also presented is a sample Radar application that includes a Joint Domain Localized (JDL) Space Time Adaptive Processing (STAP) algorithm.
Document Details
- Document Type
- Technical Report
- Publication Date
- May 01, 2005
- Accession Number
- ADA494918
Entities
People
- Dennis Fitzgerald
- Gerald Bright
- John Rooks
- Yassir Salama
Organizations
- ITT Corporation