Design, Fabrication and Characterization of High-Performance Silicon Nanowire Transistors

Abstract

We report the fabrication and characterization of double-gated Si nanowire field effect transistors with excellent current-voltage characteristics, low subthreshold slope ~85 mV/dec and high on/off current ratio ~10(exp 6). The Si nanowire devices are fabricated by using a self-aligned technique with standard photolithographic alignment and metal lift-off processes, enabling the large-scale integration of high-performance nanowire devices. We have also studied the effect of device structure and forming gas rapid thermal annealing on the nanowire transistor's electrical properties. We conclude that the self-aligned fabrication and non-overlapped gate-source/drain structure combined with appropriate post annealing leads to the excellent observed device performance.

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Document Details

Document Type
Technical Report
Publication Date
Aug 01, 2008
Accession Number
ADA496070

Entities

People

  • Curt A. Richter
  • Dimitris E. Ioannou
  • Hao D. Xiong
  • John S. Suehle
  • Qiliang Li
  • Xiaoxiao Zhu
  • Yang Yang

Organizations

  • George Mason University

Tags

DTIC Thesaurus Topics

  • Annealing
  • Catalysts
  • Electrical Properties
  • Electron Microscopes
  • Electronics
  • Fabrication
  • Field Effect Transistors
  • Materials
  • Metal-Semiconductor Junctions
  • Microscopy
  • Nanomaterials
  • Nanowires
  • Scanning Electron Microscopes
  • Semiconductor Devices
  • Semiconductors
  • Standards
  • Transistors

Fields of Study

  • Materials science

Readers

  • Nanoscale Plasmonic Nanotechnology
  • Semiconductor Device Technology