Master and Secondary Clock in Telecommunications Networks

Abstract

Telecommunications networks of time division switches, interconnected by digital transmission are being put into place. At each switch, each incoming bit stream is brought into its own buffer. then the clock in the switch "reads" each buffer to re-establish phase. Care must be taken to keep frequency differences between various clocks from becoming too large, other-wise buffers will under/over flow at an unacceptably high rate. Base on empirically defined data transmission requirements, one major network had determined that fractional frequency inequality between switches should be no worse than 1.7X10 to the minus 9th power.

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Document Details

Document Type
Technical Report
Publication Date
Nov 01, 1984
Accession Number
ADA497211

Entities

People

  • Allan Risley

Tags

DTIC Thesaurus Topics

  • Abstracts
  • Accuracy
  • Clocks
  • Communication Systems
  • Data Transmission
  • Frequency
  • Information Operations
  • Intervals
  • Standards
  • Time Intervals

Fields of Study

  • Computer science

Readers

  • Applied Combinatorial Optimization and Logic Circuit Design.
  • Electrical Engineering
  • Mathematical Modeling and Probability Theory.