Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

Abstract

According to the ITRS roadmap, 70 percent of the area of a typical ASIC today is memory and this increases to over 90 percent by the end of the roadmap. Yet despite the fact that ASICs are becoming more memory-intensive, commodity memory and ASIC design and manufacturing technologies are still on divergent paths. In this report, we examine methodologies for the design of Memory-Based Structured ASICs (SASICs) that include large amounts of dense, on-chip memory, as well as multiple processing cores, networks-on-chip, and I/O modules. We investigate regular fabrics as a means for designing logic circuitry compatible with the lithographic constraints imposed by the memory array for subwavelength geometries. We also develop midrange and high-level tools for exploring tradeoffs in power, area, and timing of complex, multicore SASICs. The report concludes with recommendations for follow-on work in the area of patterned ASICs.

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Document Details

Document Type
Technical Report
Publication Date
Oct 01, 2008
Accession Number
ADA499474

Entities

People

  • Jay Brockman
  • Larry Pileggi
  • Michael Niemier
  • Peter Kogge

Organizations

  • University of Notre Dame

Tags

Communities of Interest

  • Advanced Electronics
  • Energy and Power Technologies

DTIC Thesaurus Topics

  • Accuracy
  • Air Force
  • Air Force Research Laboratories
  • Application-Specific Integrated Circuits
  • Double Patterning Lithography
  • Energy Consumption
  • Fabrication
  • Field Effect Transistors
  • Field Programmable Gate Arrays
  • Geometry
  • Integrated Circuits
  • Logic Gates
  • Manufacturing
  • Microarchitecture
  • Photolithography
  • Semiconductors
  • Two Dimensional

Readers

  • Integrated Circuit Design and Technology.
  • Parallel and Distributed Computing.