Low-Power, High-Resolution 3D Sonar Imaging System

Abstract

SONOELECTRONICS PROGRAM LOW-POWER, HIGH-RESOLUTION 3D SONAR IMAGING SYSTEM. OBJECTIVE: - DEVELOP HIGH-RESOLUTION, LOW-POWER LOW-COST, HAND-HELD SONAR IMAGER BASED ON SPARSE ARRAY CONCEPT - 128 X 128 PIXEL IMAGE @ 400 (2D) FRAMES/s or 4 (3D rendered) FRAMES/s WITH 1 cm CROSS-RANGE & DOWN-RANGE RESOLUTION - FULLY-INTEGRATED ELECTRONIC BEAMFORMING. APPROACH: - STATE-OF-THE-ART 2D SPARSE ARRAY (TETRAD) - BANDWIDTH SELECTION IMPROVING SIGNAL TO SIDELOBE RATIO (NUWC) - LOW-POWER, HIGH-THROUGHPUT CHARGE-DOMAIN ELECTRONIC BEAMSTEERING/BEAMFORMING (TERATECH) - ICs MANUFACTURABLE IN CMOS FOUNDRY (TERATECH). ACHIEVEMENTS: - WIDEBAND SPARSE ARRAY SIMULATION with 40 dB SIGNAL-TO-SIDELOBE RATIO -PROCESSING AND COMPONENT DEVELOPMENT 32-CHANNEL 1D TIME-DOMAIN BEAMFORMING 5 BILLION OPs/s @ 1 WATT. MILESTONES: - SPARSE ARRAY WITH 32 ACTIVE ELEMENTS (7/99) - SPARSE ARRAY WITH 128 ACTIVE ELEMENTS - 128-ELEMENT SUBARRAY MODULE DEMO - 20X20 cm 2D SPARSE ARRAY WITH ELECTRONIC BEAMFORMING - 20X20 cm 2D SPARSE ARRAY WITH ELECTRONICS SYSTEM DEMONSTRATION.

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Document Details

Document Type
Technical Report
Publication Date
Aug 25, 1999
Accession Number
ADA513108

Entities

People

  • Alice M. Chiang
  • John Impagliazzo
  • Steven R. Broadstone

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Abstracts
  • Acquisition
  • Algorithms
  • Bandpass Filters
  • Bandwidth
  • Beam Steering
  • Charge Transfer
  • Data Acquisition
  • Delay Lines
  • High Resolution
  • Information Operations
  • Rhode Island
  • Sidelobes
  • Simulations
  • Test Facilities
  • Time Domain
  • Undersea Warfare

Fields of Study

  • Engineering

Readers

  • Acoustical Oceanography.
  • Image Processing and Computer Vision.
  • Integrated Circuit Design and Technology.

Technology Areas

  • Microelectronics