A Scratchpad Memory Allocation Scheme for Dataflow Models

Abstract

Scratchpad memories are alternatives to caches in real-time embedded processors. They provide better timing predictability and lower energy consumption. However, program code and data must be explicitly moved in the memory hierarchy. Current practice either leaves it up to the programmer to manually manage the memory or to use low-level compiler techniques to create an allocation schedule. In this paper, we show how to leverage the structure and semantics of a dataflow model to make optimal use of scratchpads. We assume the heterochronous dataflow model of computation (or its special cases). To show feasibility of the approach, we formulate an ILP problem to minimize the memory access times. We provide performance comparisons between our memory allocation scheme and caches with LRU replacement policy.

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Document Details

Document Type
Technical Report
Publication Date
Aug 25, 2008
Accession Number
ADA518569

Entities

People

  • Edward A. Lee
  • Hiren D. Patel
  • Shamil Bandyopadhyay
  • Thomas H. Feng

Organizations

  • University of California, Berkeley

Tags

DTIC Thesaurus Topics

  • Access Time
  • Algorithms
  • Coding
  • Computer Programming
  • Computer Programs
  • Computer Science
  • Computers
  • Electrical Engineering
  • Embedded Systems
  • Energy Consumption
  • Integer Programming
  • Linear Programming
  • Military Research
  • Optimization
  • Production Rate
  • Rate Of Consumption
  • Scratchpad Memories

Fields of Study

  • Computer science

Readers

  • Parallel and Distributed Computing.