The MasPar MP-1 As a Computer Arithmetic Laboratory

Abstract

This paper is a blueprint for the use of a massively parallel SIMD computer architecture for the simulation of various forms of computer arithmetic. The particular system used is a DEC/MasPar MP-1 with 4096 processors in a square array. This architecture has many advantages for such simulations due largely to the simplicity of the individual processors. Arithmetic operations can be spread across the processor array to simulate a hardware chip. Alternatively they may be performed on individual processors to allow simulation of a massively parallel implementation of the arithmetic. Compromises between these extremes permit speed-area tradeoffs to be examined. The paper includes a description of the architecture and its features. It then summarizes some of the arithmetic systems which have been, or are to be, implemented. The implementation of the level-index and symmetric level-index, LI and SLI, systems is described in some detail. An extensive bibliography is included.

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Document Details

Document Type
Technical Report
Publication Date
Jan 01, 1996
Accession Number
ADA531049

Entities

People

  • Daniel W. Lozier
  • Michael A. Anuta
  • Peter R. Turner

Organizations

  • United States Naval Academy

Tags

Communities of Interest

  • Advanced Electronics

DTIC Thesaurus Topics

  • Algorithms
  • Arithmetic
  • Arithmetic Units
  • Computations
  • Computer Programming
  • Computer Science
  • Computers
  • Error Analysis
  • Language
  • Mathematics
  • Numerical Analysis
  • Parallel Computing
  • Parallel Processing
  • Real Numbers
  • Simulations
  • Standards
  • United States Naval Academy

Readers

  • Computer Engineering
  • Parallel and Distributed Computing.
  • Systems Analysis and Design