Parallelizing SHA-256, SHA-1 and MD5 and AES on the Cell Broadband Engine

Abstract

The Cell BE Architecture connects a Power processor with several "synergistic processing units" via a high-speed bus, allowing parallel processing on a chip. Architectural features enabling high speed performance include SIMD, many wide registers, DMA provisions, and dual-issue instructions. We have developed extraordinarily high performance implementatioins of SHA-256, SHA-1 and MD5 for this architecture. We have also developed parallelized implementations of AES Encryption.

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Document Details

Document Type
Technical Report
Publication Date
Oct 25, 2010
Accession Number
ADA531246

Entities

People

  • Bruce Allen
  • David Canright
  • George Dinolt
  • Simson Garfinkel

Organizations

  • Naval Postgraduate School

Tags

Communities of Interest

  • Materials and Manufacturing Processes

DTIC Thesaurus Topics

  • Abstracts
  • Algorithms
  • Computer Science
  • Computers
  • Computing System Architectures
  • Contracts
  • Cryptography
  • Data Processing
  • Data Transmission
  • Department Of Defense
  • Governments
  • Instructions
  • Iterations
  • Lessons Learned
  • Parallel Computing
  • Parallel Processing
  • Pipelines

Readers

  • Computer Programming and Software Development.
  • Parallel and Distributed Computing.