Novel Memory Structure for 4 K Operation with Interfacing to Josephson Digital Circuits
Abstract
The research under this grant is a part of the realization of a hybrid Josephson-CMOS memory which will operate at 4 K and will provide the random access memory needed for digital computation by the ultra-high speed superconducting logic circuits. Standard CMOS circuits work about 40% faster at 4 K than at room temperature and are far denser than superconducting circuits so a large amount of memory can be made available. During this grant period, we have designed a CMOS memory by professional standards. We have focused on the key task of amplifying the Josephson millivolt signals to volt level as required by the CMOS memory. In particular, we have designed a sensitive CMOS amplifier with the appropriate Josephson preamplifier. Testing during this period has revealed that the almost infinite charge retention time observed in 350 nm CMOS devices does not appear in 180 nm devices due to leakage; this has led to extensive reconsiderations in our design. In the next design we will use standard SRAM cells which can function independent of leakage. We will also used a biasing circuit which is not degraded by leakage.
Document Details
- Document Type
- Technical Report
- Publication Date
- Aug 16, 2010
- Accession Number
- ADA534898
Entities
People
- Theodore Van Duzer
Organizations
- University of California, Berkeley